1. Field of the Invention
The present invention relates to an inverter drive device that drives on and off a semiconductor switching element provided in an inverter output stage and controlling current output to a load, and relates to a semiconductor module in which the inverter drive device and semiconductor switching element are integrally included.
2. Description of the Background Art
An inverter 10 that drives a single-phase motor, 3-phase motor, or the like, includes in an output stage thereof a semiconductor switching element SW that controls current output to a load, and is configured to include an inverter drive device 1 that drives the semiconductor switching element SW on and off. FIG. 3 is a diagram showing a schematic configuration of the inverter 10, which drives a 3-phase motor M acting as a load, wherein the inverter 10 includes, as the semiconductor switching element SW, upper arm IGBTs (insulated gate bipolar transistors) 2u, 2v, and 2w and lower arm IGBTs 3u, 3v, and 3w, totem pole connected and driven on in a complementary way, in a U-phase, V-phase, and W-phase respectively. Freewheeling diodes 4u, 4v, 4w, 5u, 5v, and 5w are connected in anti-parallel between an emitter and collector of the upper arm IGBTs 2u, 2v, and 2w and lower arm IGBTs 3u, 3v, and 3w respectively.
Herein, the totem pole connection of the upper arm IGBTs 2u, 2v, and 2w and lower arm IGBTs 3u, 3v, and 3w indicates a circuit configuration wherein the emitters of the upper arm IGBTs 2u, 2v, and 2w are connected to the collectors of the lower arm IGBTs 3u, 3v, and 3w respectively. Each series circuit of the totem pole connected upper arm IGBTs 2u, 2v, and 2w and lower arm IGBTs 3u, 3v, and 3w forms a half-bridge circuit.
Also, the inverter drive device 1 includes upper arm drive circuits (HVICs) 6u, 6v, and 6w, which drive the upper arm IGBTs 2u, 2v, and 2w respectively on and off, and a lower arm drive circuit (LVIC) 7, which drives each of the lower arm IGBTs 3u, 3v, and 3w on and off. The upper arm drive circuits 6u, 6v, and 6w and lower arm drive circuit 7 take in control signals, specifically U-phase, V-phase, and W-phase PWM (Pulse Width Modulation) signals, provided individually from a control device CONT formed of, for example, a PWM controlling microcomputer, thereby driving the upper arm IGBTs 2u, 2v, and 2w and lower arm IGBTs 3u, 3v, and 3w on and off with predetermined phase differences.
Also, a current detecting resistor RS is interposed in a power supply path of the semiconductor switching element SW formed of the totem pole connected upper arm IGBTs 2u, 2v, and 2w and lower arm IGBTs 3u, 3v, and 3w. The current detecting resistor RS detects voltage proportional to current flowing in the inverter 10 as current information, and the detected current information is input into each of the control device CONT and lower arm drive circuit 7.
For example, an abnormality such as an interphase short circuit, caused by an insulation failure or incorrect wiring in output wiring of the inverter 10, is detected from the current information. In particular, the lower arm drive circuit 7 includes an overcurrent protection function that immediately and directly turns off the lower arm IGBTs 3u, 3v, and 3w when an excessive current is detected, thereby interrupting the current flowing into the lower arm IGBTs 3u, 3v, and 3w. Also, the control device CONT includes an overcurrent protection function that outputs control current information to the upper arm drive circuits 6u, 6v, and 6w when an excessive current is detected, whereby the upper arm IGBTs 2u, 2v, and 2w respectively are controlled so as to be turned off.
Herein, a simple description will be given of the upper arm drive circuits 6u, 6v, and 6w and lower arm drive circuit 7 in the inverter drive device 1. FIG. 4 is a schematic configuration diagram wherein the inverter drive device 1 of a single phase, in this case the U-phase, of the inverter 10 is extracted. The inverter drive devices 1 of the V-phase and W-phase are configured in the same way.
The upper arm drive circuit 6 (6u, 6v, 6w) includes a P-MOS (P-type Metal-Oxide-Semiconductor) 8a and N-MOS (N-type Metal-Oxide-Semiconductor) 8b, connected in series and driven on and off in a complementary way, as output stage transistors that drive the upper arm IGBT 2u (2v, 2w) on and off. Herein, the output stage transistors formed of the P-MOS 8a and N-MOS 8b drive the upper arm IGBT 2u (2v, 2w) on and off by being turned on and off in a complementary way, with voltage at a connection point of the totem pole connected upper arm IGBT 2u (2v, 2w) and lower arm IGBT 3u (3v, 3w), that is, an intermediate voltage Vs, as a reference potential.
Also, the upper arm drive circuit 6 (6u, 6v, 6w) includes an input filter 8c that takes in a control signal (PWM signal) provided from the control device CONT, and a level shifting circuit 8d that shifts the level of the control signal (PWM signal) taken in via the input filter 8c to the level of the output stage transistor operation reference potential. Further, the upper arm drive circuit 6 (6u, 6v, 6w) is configured so as to drive the output stage transistor (P-MOS 8a, N-MOS 8b) on and off using the control signal (PWM signal) whose level has been shifted by the level shifting circuit 8d. 
When the control device CONT detects an occurrence of an overcurrent from the current information (detected voltage) detected via the current detecting resistor RS, the control device CONT stops the output of the control signal (PWM signal). Because of this, the drive of the P-MOS 8a and N-MOS 8b stops, and the upper arm IGBT 2u (2v, 2w) is controlled so as to be forcibly turned off.
Meanwhile, the U-phase (V-phase, W-phase) of the lower arm drive circuit 7 includes a P-MOS 9a and N-MOS 9b, connected in series and driven on and off in a complementary way, as output stage transistors that drive the lower arm IGBT 3u (3v, 3w) on and off. The output stage transistors formed of the P-MOS 9a and N-MOS 9b drive the lower arm IGBT 3u (3v, 3w) on and off by being turned on and off in a complementary way, with a ground potential GND as a reference potential.
Also, the lower arm drive circuit 7 includes an input filter 9c that takes in a control signal (PWM signal) provided from the control device CONT, and an AND gate circuit 9d that controls output to the output stage transistor (P-MOS 9a, N-MOS 9b) of the control signal (PWM signal) taken in via the input filter 9c. The AND gate circuit 9d performs a role of driving the P-MOS 9a and N-MOS 9b on and off in a complementary way by outputting the control signal (PWM signal) to the output stage transistor (P-MOS 9a, N-MOS 9b) only when an output of a latch circuit 9e is at “H”.
Herein, the current information (detected voltage) detected via the current detecting resistor RS is provided to a comparator 9f, and compared with a predetermined reference voltage 9g. When the detected voltage exceeds the reference voltage 9g, the comparator 9f detects this as an occurrence of an overcurrent, and sets the output of the latch circuit 9e at “L”. By the output of the latch circuit 9e being set at “L” due to the overcurrent detection, the AND gate circuit 9d is closed, and the drive of the output stage transistor (P-MOS 9a, N-MOS 9b) by the control signal (PWM signal) is forcibly prohibited. As a result of this, the lower arm IGBT 3u (3v, 3w) is controlled so as to be forcibly turned off when an overcurrent is detected.
Herein, the inverter 10 configured to include the inverter drive device 1 configured as heretofore described is such that when, for example, an interphase short circuit occurs in the output wiring and an overcurrent (short circuit current) flows, the lower arm drive circuit 7 promptly detects the occurrence of the overcurrent, and controls the lower arm IGBTs 3u, 3v, and 3w so as to be turned off. Meanwhile, the control device CONT detects an occurrence of an overcurrent (short circuit current), and stops the main power of the control signal (PWM signal), because of which it cannot be denied that there is a slight delay in the upper arm drive circuits 6u, 6v, and 6w controlling the upper arm IGBTs 2u, 2v, and 2w so as to be turned off.
Herein, when the upper arm IGBTs 2u, 2v, and 2w and lower arm IGBTs 3u, 3v, and 3w are forcibly turned off, a reflux current flows into the upper arm IGBTs 2u, 2v, and 2w due to an inductance component existing in internal wiring of the upper arm drive circuit 6 (6u, 6v, 6w). As the current flowing immediately before the upper arm IGBTs 2u, 2v, and 2w and lower arm IGBTs 3u, 3v, and 3w are controlled so as to be forcibly turned off is an overcurrent (short circuit current), the reflux current flowing at this time is ten times or more greater than a reflux current flowing when the inverter operates normally.
Therefore, an amount of current change (−dIc/dt) when the upper arm IGBTs 2u, 2v, and 2w are forcibly turned off is 1,000 A/μs or more, which is ten times or more greater than the amount of current change (−dIc/dt) at a time of normal operation. As a result of this, a counter electromotive force caused by the inductance component existing in the internal wiring and the amount of current change (−dIc/dt) is applied unchanged to the upper arm IGBTs 2u, 2v, and 2w. Further, when the counter electromotive force exceeds a breakdown voltage between the collectors and emitters of the upper arm IGBTs 2u, 2v, and 2w, and a breakdown voltage between the cathodes and anodes of the freewheeling diodes 4u, 4v, and 4w, there is concern that the upper arm IGBTs 2u, 2v, and 2w will reach overvoltage breakdown.
In order to combat this kind of problem, consideration is being given to increasing the breakdown voltage between the collectors and emitters of the upper arm IGBTs 2u, 2v, and 2w and the breakdown voltage between the cathodes and anodes of the freewheeling diodes 4u, 4v, and 4w with respect to the counter electromotive force generated due to the amount of current change (−dIc/dt) when the current is interrupted. However, as the breakdown voltage between the collectors and emitters of the upper arm IGBTs 2u, 2v, and 2w and conduction loss thereof are in a trade-off relationship, a new problem occurs in that loss in the upper arm IGBTs 2u, 2v, and 2w when the upper arm drive circuit 6 (6u, 6v, 6w) operates normally increases, and the operating efficiency of the inverter 10 worsens.
With regard to this, a case wherein a clamping diode (Zener diode) ZD combating counter electromotive force and a current backflow blocking diode (reverse blocking diode) D are interposed in series between the collector and a gate of the upper arm IGBT 2u (2v, 2w), as shown by a broken line in FIG. 4, and the voltage of counter electromotive force applied to the upper arm IGBT 2u (2v, 2w) is clamped by the clamping diode ZD, is disclosed in, for example, JP-A-2009-253484.
According to the inverter 10 configured to include this kind of clamping diode ZD and reverse blocking diode D, energy of the counter electromotive force applied to the upper arm IGBT 2u (2v, 2w) can be caused to flow from the gate side of the upper arm IGBT 2u (2v, 2w) into the upper arm drive circuit 6 (6u, 6v, 6w) as breakdown current Ir of the clamping diode ZD. Therefore, voltage is generated at both ends of an equivalent internal impedance of the upper arm drive circuit 6 (6u, 6v, 6w) by the breakdown current Ir flowing into the upper arm drive circuit 6 (6u, 6v, 6w) via the clamping diode ZD, and this voltage is applied to the gate of the upper arm IGBT 2u (2v, 2w).
Therefore, the internal impedance (an equivalent gate resistance RG) of the upper arm drive circuit 6 (6u, 6v, 6w) seen from the upper arm IGBT 2u (2v, 2w) side is set so that, for example, voltage applied to the gate of the upper arm IGBT 2u (2v, 2w) exceeds an operational threshold of the upper arm IGBT 2u (2v, 2w), and a collector current flows owing to a saturated operation of the upper arm IGBT 2u (2v, 2w). Therefore, the upper arm IGBT 2u (2v, 2w) is turned on in a saturated operation state, because of which the energy of the counter electromotive force applied to the upper arm IGBT 2u (2v, 2w) flows via the upper arm IGBT 2u (2v, 2w).
As a result of this, the energy of the counter electromotive force can be consumed as heat energy by the upper arm IGBT 2u (2v, 2w). Consequently, the voltage of the counter electromotive force applied to the upper arm IGBT 2u (2v, 2w) can be restricted by the clamping diode ZD, whereby overvoltage breakdown of the upper arm IGBT 2u (2v, 2w) can be effectively prevented.
Note that in order for the upper arm IGBT 2u (2v, 2w) to be turned on in a saturated operation state, a voltage of approximately 6V is needed as a gate voltage thereof. Also, the internal impedance (equivalent gate resistance RG) of the upper arm drive circuit 6 (6u, 6v, 6w) is generally in the range of 10 to 50Ω. Therefore, in order to obtain a gate voltage of approximately 6V, the breakdown current Ir flowing via the clamping diode ZD needs to be a maximum of 600 mA. Therefore, in order to reduce a clamping operation resistance of the clamping diode ZD, it is necessary to secure a chip area of the same extent as that of the upper arm IGBT 2u (2v, 2w) as the clamping diode ZD, and problems occur in that circuit area increases, system cost increases, and the like.
Meanwhile, when envisaging a clamping diode ZD of a small chip area that can conceivably be embedded in the chip of the upper arm drive circuit 6 (6u, 6v, 6w), the breakdown current Ir flowing into the clamping diode ZD decreases to an amount close to, for example, 100 μA. Therefore, in order to generate a gate voltage of approximately 6V when the upper arm IGBT 2u (2v, 2w) is turned on in a saturated operation state, it is necessary that the internal impedance (equivalent gate resistance RG) of the upper arm drive circuit 6 (6u, 6v, 6w) is of an amount close to, for example, 60 kΩ.
When increasing the internal impedance of the upper arm drive circuit 6 (6u, 6v, 6w) in this way, switching loss in the upper arm IGBT 2u (2v, 2w) when the inverter 10 is operating normally increases. Further, the amount of heat generated in accompaniment to the upper arm IGBT 2u (2v, 2w) being turned on increases, and a switching operation at or above 10 kHz, which is a general switching frequency in the inverter 10, is difficult.